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title{{bf What does the HP Teramac have to do with Moletronics?}}

author{{em Nan Zhang }\

\

Department of Computer Science \

Michigan State University \

East Lansing, MI 48824\

{tt nanzhang@cse.msu.edu}\

\

}

date{empty}

maketitle

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section{Introduction}

label{SE:intro}

Recently, one of the main microprocessor manufacturer Intel Corp.

announced that a bug within a small number of their Coppermine

microprocessors had been found. And this was not the first time

Intel presented similar announcement. Also, another CPU giant AMD

has been suffered from design and manufacture defect in their

microprocessors for a long time.

The traditional paradigm for computer hardware is to design the

specific circuit including the gates, wires and the way they

connected, and built it perfectly. Perfection of the components is

the baseline of modern computer hardware--a single design or

manufacture defect can cause the entire system crashed. It is

thought that with the chip's increasing of complexity and

shrinking in size, the defect is inevitable, either in design or

manufacture process. An observation that is sometimes called

Moore's second law alleged that the cost of integrated circuits

factories are escalating exponentially with time for attempting to

keep perfection of chips. Then by the year 2012, a single

fabrication plants could cost up to 30 billion dollars.cite

{Teramac98}

As we know, the next generation electronic technology--Moletronics

is a promising way to design faster and more powerful computers.

Computers by moletronics technology is typically constructed by

random chemical and physical procedures, thus the defect in final

product is inevitable. For Moletronics, it is even harder and

economically infeasible to keep all its component perfect. It is

seemed that even though finally we can make out a prototype of

Moletronics computer, the high price will keep most of the users

out of the door.

The resolution to this problem may come from a newly developed

prototype supercomputer in HP, called Teramac. Although the

architecture of the prototype is built on conventional electronic

method. Its principles and approaches will apply a great impact on

Moletronics technique.

section{Basic Concepts}

label{SE:concepts}

The name "Teramac" comes from the word "Tera" which means

"Trillion" or ${10^{12}}$, and "mac" from "Multiple Architecture

Computer". The key point that Teramac differs from conventional

computer architecture is its tolerance to defect. It is evaluated

that there are 200,000 defects in this computer, but surely it

works! And yet it could run in some of its configurations 100

times faster than a single processor workstation.

The key property of Teramac is its "software-changeable

architecture" feature. That is to say we can use code or

instruction to change the logic composition of Teramac. It is why

we call it "Custom Configurable Computer (CCC)".

Teramac consists of 864 identical chips named "field programmable

gate array" (FPGA). Each FPGA contains a large quantity of

computation units and a flexible connection network, which are

called LUTs and Crossbar, respectively. All the LUTs are identical

for their physical structure and can implement different logic

function. So they do not consist of digital logical component like

AND gate, buy rather with memory. "LUT", whose name comes from

Look-Up Table, is a 64-bit memory block that hold 6 address lines

as input and one bit output according to the memory's content.

Then, depending on the content of the memory, LUT can perform

${2^{64}}$ kinds of logic functions. There are 65,536 LUTs in the

Teramac. About 30% of the FPGAs(256 out of 864) are contributed

to the computation units--LUTs, and others are used for inner

connecting and signal routing. That is the function of Crossbar.

Crossbar can be considered as a wiring network whose connection

can be dynamically changed. An Crossbar network contains two

planes of crossbars. one is the date line crossbar, the other is

the address line crossbar. Actually, data line crossbar is an

array of switches connecting the cross of each rows and column.

Memory line crossbar contains an array of memory bits that can

control the status of each switches at the corresponding position.

Then we can manipulate the data line connection by setting the

memory plane with different bits. So the basic components of the

Teramac could all be programmable. The use of FPGAs allow us to

load a desired custom architecture onto Teramac through

configuration of the memory. Teramac uses a 300-megabit word

called very long instruction word (VLIW) for the presentation of

desired architecture, most of which are bits for Crossbar

configuration.

section{Why Teramac architecture helps to Moletronics}

label{SE:defect}

The capacity of fault tolerance of Teramac comes from its

redundant design. Considering a Crossbar network. There are couple

of pathways between two arbitrary cross section. Even if the

network has a physical defect in its circuits, we could also find

a different pathway, thus, a different VLIW to bypass the defect.

The innate redundancy and defect tolerance property of Teramac is

very important to the Moletronics technique. Producing the defect

free products is costly. As an example, it is always far more

expensive for purchasing a perfectly reliable disk than a

redundant disk array. For the Moletronics products, the situation

is even worse. Building the perfect product, in some aspect, is

impossible. Thus, using the Teramac architecture to build a

defected but workable system is a feasible way.

Furthermore, beside defect tolerance, Teramac also contributes

other advantages to Moletronics. We learned that Teramac has a

homogeneous physical structure. The LUTs and Crossbars a all the

same in each FPGAs. Undoubtedly, it will great reduce cost of the

whole system.

section{Conclusion}

label{SE:conclusion}

The Teramac illustrates a totally different paradigm in system

design. Comparing to traditional method, it tremendously decrease

the cost of the system and make it more flexible.

begin{thebibliography}{99}

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bibitem{Teramac98}

James R. Heath, Philip J. Kuekes, Gregory S. Snider and R. Stanley

Williams, A Defect-Tolerant Computer Architecture: Opportunities

for Nanotecjnology, in {em SCIENCE }, Vol.280 June, pp.1716-1721,

1998.

bibitem{Teramac96}

W. Bruce Culbertson etc. The Teramac Custom Computer: Extending

the Limites with Defect Tolerance, in {em Proceedings of the IEEE

Internation Symposium on Defect and Fault Tolerance in VLSL System

}, 1996.

bibitem{Teramac97}

W. Bruce Culbertson etc., Defect Tolerance on the Teramac Custom

Computer, in {em Proceedings of the IEEE Symposium on FPGAs for

Custom Computing Machine},1997.

end{thebibliography}

end{document}

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